本次美国代写主要为模拟CMOS集成电路相关的project
(a) You can work individually or in groups of two. Only one report is required
for each group
(b) PROJECT FILE SHOULD BE <YourName> Project ECE520.pdf
(c) Collaboration and discussion about project between teams is encouraged but please
make sure that each team writes up the report on its own.
1. Design a di erential input di erential output op-amp with capacitive feedback as
shown in Fig. 1. Achieve the following speci cations while minimizing power consumption
Closed-loop gain 5 (absolute not dB)
Load Capacitance 2 pF
Settling time 40 nS for 0.01% settling
Supply Voltage 1.8 V
HD3 (Closed-loop) -50 dB
What is the HD2 and HD3 during open-loop and closed-loop operation?
Note: The only ideal supplies allowed in the design are (a) VDD = 1.8V or
lower, (b) One reference current source of 100 A.
Please report the following –
(a) Quantitative design approach and justi cation for device sizes and tradeo s.
(b) Clear schematics with annotated DC voltages and bias currents through devices along
with the operating points such as VDS and VGS.
(c) Simulated AC performance in open loop, simulated AC performance in closed loop,
simulated common-mode to di erential-mode rejection ratio
(d) Transient sim with positive and negative step responses with settling time.
(e) Simulation of HD2 and HD3 using transients.
(f) Tar of your cadence library.
