本次北美CS代写主要是使用assembly汇编程序E20实现缓存
CS-UY 2214 — Homework 7
Unless otherwise specified, put your answers in a plain text file named hw7.txt. Number each answer. Submit your work on Gradescope.
You may consult the E20 manual, which is available on Classes, under the Resources tab, in the “guides” folder.
Problems
- Write an E20 assembly language program that will store the value 1099 at memory cell 456, then halt. Make sure that your program is correct and can be assembled.
- We have a processor with a single cache. Every cache access (whether it results in a hit or a miss) takes 4ns. Accessing main memory takes 40ns. A particular program executes a series of lw instructions, during which it experiences a 98% hit rate. What is the processor’s average time per lw?
- In this class, we’ve discussed computer architecture primarily from the perspective of a single-processor system: that is, we assume that each computer has exactly one processor. In today’s world, most computers have multiple processors, each of which is capable of operating independently of the others. Each processor can concurrently run a different program. Often, these processors will share RAM, but will each have their own cache.Consider the following architecture, where the computer has four processors, each with their own L1 cache:
Your task is to discuss the choice between write-back and write-through cache in such a multiprocessor architecture. Specifically address any potential problems or complications that may arise by using one or the other of these two write policies. Also discuss a possible strategy to mitigate said complications.
4. Consider a 3GHz processor that has 64-bit addresses. It has 512KB of L1 cache (excluding tags and valid bits) and 4MB of L2 cache (also excluding tags and valid bits). All blocks are 512 bytes. Both caches are direct-mapped. Assume that each memory cell is one byte.
- (a) What is the size of the the tag, in bits, for each of the caches?
- (b) What is the total actual size (in bits) of each of the caches, including block storage, valid bits, and tags?
- (c) We define “miss penalty” as the difference in speed between a cache hit and a cache miss. We define a “cache reference” as an attempt to access as a cache, which may result in either a hit or a miss.
In this question, a “non-memory instruction” refers to an assembly language instruction that does not access memory, such as addi or jal; as opposed to a “memory instruction,” such as lw or sw. Assume that non-memory instructions and L1 cache hits execute in one cycle. L2 cache hits carry a 10ns penalty, and main memory accesses carry an 100ns penalty. Assume that 10% of instructions result in an L1 reference (an attempt to access the L1 cache); 5% of all instructions result in an L2 reference; and 3% of all instructions go to main memory.Calculate the average cycles per instruction (CPI).
5. A particular program executes a sequence of reads at the following memory byte addresses (in hex):
40 47 50 42 81 83 85 57 46
We have a cache with a capacity of 32 bytes (not including metadata, such as tags and valid bits). For each of the following cache types, assume that the above sequence of memory accesses is made. For each memory access in each cache, show whether it is (a) a cache hit (H), (b) a cache miss resulting in an eviction (M), or (c) a cache miss not resulting in an eviction (MC). Then give the hit ratio (i.e. the number of hits per total number of memory accesses) for each cache.
Each memory cell is one byte.
All associative caches use an LRU replacement policy.
(a) direct mapped cache, block size = 4 bytes
Addr 40h 47h 50h 42h 81h 83h 85h 57h 46h H, M, or MC?
Hit ratio:
(b) fully associative cache, block size = 4 bytes
Addr 40h 47h 50h 42h 81h 83h 85h 57h 46h H, M, or MC?
Hit ratio:
(c) direct mapped cache, block size = 8 bytes
Addr 40h 47h 50h 42h 81h 83h 85h 57h 46h H, M, or MC?
Hit ratio:
(d) two-way set associative cache, block size = 8 bytes
Addr 40h 47h 50h 42h 81h 83h 85h 57h 46h H, M, or MC?
Hit ratio:
6. Consider a computer with two caches:
