本次代写主要为数字电路相关的限时测试

1. Design a digital system working as a two-way routing element with rotating priority. The system receives in parallel at each clock cycle two input data that
must be forwarded to the two outputs either in the same order or in the swept order. Each input data is accompanied by one bit that indicates the preferred
output. The two received inputs data are forwarded according to their preferred output, if there is no conflict, i.e., the preferred outputs of the two inputs
are different from each other. In case of conflict, the input with the highest priority is forwarded to its preferred output, while the other input is forwarded
to the available output, by ignoring the preferred choice. The priority is not fixed, but it is updated based on the following policy:

A. Initially, the priority is given to the first input.

B. The circuit maintain the initial priority for three conflicts. Therefore, when a conflict is occurring, the preferred output is given to the first output
for three times. If these conflict events are interleaved with cycles without conflict, the outputs are assigned according to the preferred choices
and the priority is not used to drive the decision.

C. After three conflict events, the priority is assigned to the second input, which will gain the preferred output for the three following conflicts.

D. Then, the priority is granted again to the first input and so on, by alternating three conflicts with priority assigned to the first input and three
conflicts with the priority given to the second input.

Inputs: clock CK, asynchronous reset RST, enable signal E, input data DIN0 and DIN1, preferred output, A0 and A1 for input 0 and input 1 respectively.

Outputs: output data DOUT0 and DOUT1.

Description: After the reset, at every clock cycle, if the E signal is high, two new data are received on inputs DIN0 and DIN1. The preferred destinations A0 and A1 are associated to the received inputs. For example, if A0=1, this means that the preferred destination for data on DIN0 is the output DOUT1. These data are
routed across the system towards the outputs according to the A0 and A1 values. In case of conflict (A0=A1), the current priority is used to decide how to route
the received inputs, and then the priority is updated as described above. At any cycle, if the E signal becomes low, the status of the routing system is frozen,
no new data are routed, and no output is updated. When the E signal becomes 1 again, the system resumes.
Requested elements:

A. Draw the datapath of the system at the RTL level, by using elementary components, such as registers, adders, … In the drawing, for
each datapath component, clearly show input and output signals, as well as control signals.

B. Type a list of at least two datapath components and for each of them provide:
1. Input connections (i.e. name of the components or ports connected as inputs to the considered component)
2. Output connections (i.e. name of the components or ports connected as outputs to the considered component)

C. Type a brief description of the processing implemented by the datapath.

D. List control and status signals

E. Draw the state diagram of a FSM implementing the control unit of the router.

F. Type the VHDL code of the CC1 circuit that generates the future state of the FSM.