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VHDL代写 | CSE 260M Laboratory #5

VHDL代写 | CSE 260M Laboratory #5



CSE 260M Laboratory #5

In this laboratory, you will implement an embedded RSRC computer system starting with
VHDL models for the RSRC CPU (rsrc.vhd) and associated subcomponents, a Read-Only
Memory (eprom.vhd), a Static Random-Access Memory (sram.vhd), and an I/O “PINS”
module (pins.vhd). The top level module, testbench.vhd, is a hierarchical “wrapper” that
“wraps up” these components into an embedded RSRC system for the Digilent Artix-7
development board. Each of these components, as well as the assembly language syntax for the
RSRC CPU, the memory map for the embedded system, etc., will be discussed in detail during
class lectures.

The machine language program in eprom.vhd supplied by the instructor computes the peak
value of the polynomial from Labs 1-4 and displays the result in hexadecimal on the 7-segment
display on the development board using the logic inside the PINS module. The assembly source
code used to produce eprom.vhd is shown below:

.org 0 ; Program starts at address 0
la r30,PINS ; IO addresses to r30
la r31,TOP ; r31 holds the loop address
la r1,0 ; Initialize difference engine coefficients
lar r2,1000001
la r3,-6
la r4,-30
la r5,-24
TOP: add r1,r1,r2 ; Update the difference engine values
add r2,r2,r3
add r3,r3,r4
add r4,r4,r5
brpl r31,r2 ; Branch conditionally to TOP testing for peak

nop ; Replace with bin2bcd r1,r1

st r1,0(r30) ; Display the lower 8 BCD digits


.org -4
PINS: .dw 1

In this laboratory, you will modify the appropriate RSRC source files to add a new instruction,
bin2bcd, to the RSRC instruction set with the following syntax:

bin2bcd ra,rc

You will then replace the NOP instruction in the eprom.vhd file with a hand-assembled
machine code for the instruction (use OP Code 00111 for the bin2bcd instruction)