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Verilog代写 | CSE 1401L Lab 4-5

Verilog代写 | CSE 1401L Lab 4-5

本次Verilog代写的主要内容是奇偶校验位的实现
CSE 1401L Lab 4-5.  Error correction

Lab 4: (forward error correction block coder/transmitter): Given a series of fifteen 11-bit message blocks in data mem[0:29], generate the corresponding 16-bit (2-byte) encoded versions and store these in data mem[30:59]. Input and output formats are as follows:

            

input MSW = 0   0   0   0   0   b11 b10 b9

LSW =  b8 b7 b6 b5 b4 b3   b2   b1, where bx denotes a data bit

 

    output MSW =  b11 b10 b9 b8 b7 b6 b5 p8

LSW =  b4   b3  b2 p4 b1 p2 p1 p0, where px denotes a parity bit

 

          Example, to clarify “endianness”:  binary data value = 10101010101

mem[1] = 00000101   — 5 bits zero pad followed by b11:b9

mem[0] = 01010101   — lower 8 data bits b8:b1

 

You would generate and store:

mem[31] = 10101010 — b11:b5, followed by p8

 

p8 = ^(b[11:5]) = ^1010101 = 0;

 

p4 = ^(b11:b8,b4,b3,b2) = ^1010_010 = 1;

 

p2 = ^(b11,b10,b7,b6,b4,b3,b1) = ^10_10_01_1 = 0;

 

p1 = ^(b11,b9,b7,b5,b4,b2,b1) = ^1_1_1_10_01 = 1;

             

              p0 = ^(b11:1,p8,p4,p2,p1) = parity of all data and the other 4 parities – 0

 

mem[30] = 01011010 =  b4:b2, p4, b1, p2, p1, p0

 

Note that you may read or write only one byte at a time in data memory, so you will need two read (load) cycles to bring the raw 11-bit data in for processing, and two write (store) cycles to put the result into data memory.

 

 

You will need a data_memory, a register file (cache), an ALU, a program counter, an instruction (machine code) memory, and some way to parse your instructions into reg_file address pointers, ALU instructions, and reg_file and data_memory write enables. Any muxes will need control bits, as well.

 

Lab 5: (forward error correction block decoder/receiver): Given a series of 15 two-byte encrypted data values, possibly corrupted in data mem[64:93], recover the original message and write into data mem[94:123].

 

This is just (sort of 🙂 ) the inverse problem. However, in Lab 4 there was only 1 unique output for each unique input. Now there are several (how many?) possible inputs for each of the 2**11 possible outputs. This code can correct any single-bit error and detect any two-bit error. The test bench will generate parity bits for various random data sequences, occasionally flip one, occasionally two, of the parity or data bits, and then ask you to figure out the original message.

 

Your ouput should be as follows (where ? = wild card or don’t care — the test bench will not look at this part of your result at all):

 

16’b10000???_????????:  two-bit error encountered (correction not possible)

16’b01000abc_defghijk: one-bit error found and corrected; original 11-bit message was 16’b00000abc_defghijk

16’b00000abc_defghijk: no error detected in either data or parity; original 11-bit message was 16’b00000abc_defghijk

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