这是一个美国的Verilog集成电路作业代写

1. Using DC simulations, plot the Gate characteristics (Drain Current on Y-axis
Vs Gate Voltage on X-axis) on a linear and log scale (Y-axis) of the following
Transistors whose models are available in the ASAP 7nm PDK provided. Assume a
Supply Voltage, VDD = 0.7V and a width of ‘3 fins’ for each of the
transistors (i) – (iii) and a width of 1 fin for SRAM NFET and a
width of 1 fin for the SRAM PFET

(a) From the Gate characteristics, extract the VT of each of the Transistors for
the 2 cases of VDS = 10mV and 0.7V

NFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM
PFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM

Show the Values of VT using a Bar diagram for NFETs and PFETs

(b) From the Gate characteristics, extract the Subthreshold Swing of each of
the Transistors for the 2 cases of VDS = 10mV and 0.7V

NFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM
PFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM

Plot the Subthreshold Swing of NFETs and PFETs as a function of VT (using results
from (a) above). Do you see a trend? If so, explain why this is so

(c) From the Gate characteristics, determine the Off-current (drain current
when VGS =0) of each of the Transistors for the 4 cases of VDS = 10mV, 100mV,
400mV and 0.7V

NFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM
PFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM

Plot the off-current of NFETs and PFETs as a function of VT (using results from (a)
above)

Plot the off-current of NFETs and PFETs as a function of VDS (using results from

(a) above) for each of the NFETs and PFETs – Does DIBL have any impact on this
trend? justify your response with percentage increase of off-current with increase in
VDS

(d) From the Gate characteristics, determine the On-current (drain current when
VGS =0.7V) of each of the Transistors for the case of VDS = 0.7V

NFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM
PFET: (i) RVT, (ii) LVT, (iii) SLVT, (iv) SRAM

Plot the on-current of NFETs and PFETs as a function of VT (using results from (a)
above)

(e) Using the results from (c) and (d) above, calculate the on/off current
ratio for each of the Transistors below for the case of VDS = 0.7V