本次美国代写主要为MIPS相关的homework

Problems:
(1) You are a member of the design team of a newcomputer system. Your task is to nail down the last
details regarding the implementation of the cache.
Some decisions cannot be changed:
•The system is designed for programs where 65% of memory accesses are reads and 35% of
memory accesses are writes.
•The block size is 16 bytes.
•The width of the bus between the cache and main memory is 32 bits.
•The cache access time is 6ns.
•The main memory access time is 65ns.
•The write policyiswrite-back.
The remaining question has to do with the handling of a write-miss. Specifically,onawrite-miss
there are twooptions: (I) The main memory is updated but the accessed block is not copied to the
cache (write-around). (II) The block is movedtothe cache and is updated there (write-allocate).
If option (I) is chosen, the hit rate will be 90% and, on average, 70% of the blocks in the cache will be
dirty.Ifoption (II) is chosen, the hit rate will be 95% and, on average, 75% of the blocks in the cache
will be dirty.
In order to choose between options (I) and (II), youmust compute the effective access time for each
case and pick the design that will result in a lower access time.
Explain anyassumption you need to make. Explain briefly the computations you make, i.e., what is
the justification for the way you are computing the effective access time. Check your calculations
carefully — a correct decision requires correct computations.
(2) 5.17.1 in the book.
Note: Each one of the applications utilizes half of its maximum possible virtual address space.

(3) 5.17.2 in the book.
Note: The first leveltable has 256 entries. Each one of the applications utilizes half of its maximum
possible virtual address space.
(4) A virtual memory has a page size of 4096 (212
)words. There are 64 pages of virtual address space
butonly 5 (fiv e)page frames in real memory.The page table is stored in a special memory module
and does not takeupspace in real memory.The minimum-addressable unit of the CPU is one word.
The program issues the following sequence of addresses (shown here in hex):
2f012, d120, 550, d58b, 7194, 30000, 7052, 5550, 2fa02, 744, 7276
Before the program begins execution, the real memory is ‘‘empty. ’’
A) Assume that FIFO replacement is used. Circle the references that will cause a page fault.
2f012, d120, 550, d58b, 7194, 30000, 7052, 5550, 2fa02, 744, 7276
B) Assume that LRUreplacement is used. Circle the references that will cause a page fault.
2f012, d120, 550, d58b, 7194, 30000, 7052, 5550, 2fa02, 744, 7276

(5) A computer system has the following characteristics:
•The memory is byte addressable.
•The disk address where a virtual page is stored is the virtual page number.
•Processor: 65% of memory accesses are reads
The processor produces 30 bit addresses.
•Real memory: Size: 128MiB. Access time: 110 nano-seconds.
The width of the bus to memory is 64 bits.
Page size is 16KiB.
•Cache: The cache is accessed using physical addresses.
Size: 512KiB. Access time: 15 nano-seconds.
Cache block size is 64 bytes.
Organization: eight-way set-associative.
Cache hit rate: 95%.
Write policy: write-back, write-around
•TLB: Size: 256 entries. Access time: 5 nano-seconds.
Organization: direct mapped.
TLB hit rate: 98%.
A) Assume that the page fault rate is 0.1% and the average disk access time is 8 milli-seconds. Do
you nowhav e all the information you need to compute the overall average effective access time as
seen from the processor?Ifnot, specify what additional information is needed. (Note, in this
part you are not asked to actually compute an effective access time).
B) Assume that the page fault rate is 0. Compute the effective access time to the memory system.
Clearly specify anyassumptions you make.
(6) Consider abyte-addressable virtual memory system with the following properties:
•64bit virtual addresses
•8 KiB pages
•34bit physical addresses
•A sixteen-way set associative TLB that holds 1024 page-table entries.
•The page table is organized as a four leveltable.