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Mips汇编代写 | CSE 141: Homework #4

Mips汇编代写 | CSE 141: Homework #4


Q1. Show forwarding and stalls for the following code, assuming the pipelined machine from with full support for forwarding. Show it the way we did in class, with IF ID EX M WB, arrows, and bubbles.

  C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17
lw r2, 50(r12) IF ID EX M WB                        
add r6, r2, r1                                  
sub r9, r6, r8                                  
lw r1, 2000(r9)                                  
add r5, r1, r2                                  
addi r7, r9, #100                                  


Q2.We run some code on the MIPS pipeline from class with the following characteristics.  30% of instructions are loads and 25% of those are followed immediately by a use of the loaded register.   10% of instructions are branches, with 30% of the instructions in the branch delay slot being NOPs.  What is the CPI of this code?

For Q3 to Q5, refer to the following:

The importance of having a good branch predictor depends on how often conditional branches are executed. Together with branch predictor accuracy, this will determine how much time is spent stalling due to mispredicted branches. In the following questions , assume that the breakdown of dynamic instructions into various instruction categories is as follows:

40% 25% 5% 25% 5%

Also, assume the following branch predictor accuracies:

Always-Taken 2-Bit
45% 85%

Q3. Stall cycles due to mispredicted branches increase the CPI. What is the extra CPI due to mispredicted branches with the always-taken predictor? Assume that branch outcomes are determined in the EX stage, that there are no data hazards, and that no delay slots are used.

Q4.  Repeat Q3 for the 2-bit predictor.