(1) In the system described in Ed2-Chap8 pp. 665-666, the memory system takes 200 ns to read the ﬁrst
four words, and each additional four words require 20 ns. The memory system is modiﬁed so that it
takes 120 ns to read the ﬁrst four words and 15 ns to read each additional four words, ﬁnd the
sustained bandwidth and the latencyfor a read of 256 words for transfers that use 4-word blocks and
for transfers that use 16-word blocks. Also compute the effective number of bus transactions per
second for each case.
(2) Design a‘‘fair’’bus arbiter.There are four devices connected to the bus. The arbiter will have four
‘‘busrequest’’ lines as inputs. The outputs of the arbiter are four ‘‘busgrant’’ lines. When adevice
wants the bus, it asserts its bus request line. Adevice gets the bus when its bus grant line is asserted
by the arbiter.A device that gets the bus uses it for one cycle. The arbitration for anyparticular bus
cycle occurs during the previous cycle. A device that is currently using the bus can contend for use
of the bus during the next cycle. At most one device can use the bus during one cycle. Anynumber
of devices (zero to four) can contend for the bus during every cycle.
The arbiter enforces ‘‘fairness’’among the the devices by dynamically changing the relative priority
of the devices. Denote the devices: D0, D1, D2,and D3.When the system is initialized, D0 has top
priority,then D1 and D2 with D3 having the lowest priority.Note that eventhe lowest priority
device may get the bus if none of the other devices request it. When some device Di
(0 ≤ i ≤ 3) gets
the bus, the top priority is changed to device Dj
with j = (i + 1)mod4. The priority of devices is
then D(i+1)mod4, D(i+2)mod4, D(i+3)mod4,and D(i+4)mod4.
A) Design the arbiter.Your design should be at the levelofgates and ﬂip-ﬂops. Showyour work
(truth tables etc.).
B) Showatiming diagram that includes the clock, the bus request lines, the bus grant lines, and
the bus data lines for ﬁvecycles under the following conditions:
The system is initialized before the ﬁrst cycle. During the ﬁrst cycle D1 and D3 request
the bus. During the second cycle D2 requests the bus.
(3) Recall that the MIPS ISA is big endian. Consider the pipelined MIPS implementation shown in
Figure 4.60, page 328, with the enhancement for supporting lw and sw shown in Figure 4.57, page
324. In this implementation, the box labeled ‘‘Data memory’’isa230
× 32 memory — a 32-bit
word can be either read from or written to the memory in every access. Hence, the address input to
this memory consists of just 30 bits — the 30 most-signiﬁcant bits of the effective address computed
by the ALU.
Your task is to add to this implementation support for the sb (store byte) instruction, documented on
page A-676 in the book. You cannot modify the implementation of the data memory in any way.
Be sure to consider anyinteractions between the new sb instruction and the already supported
instructions that must, of course, continue to work.
Hint: In the existing implementation, for the sw instruction no useful work is done in the ﬁfth
pipeline stage. Forthe sb instruction, your implementation will require critical work to be
performed in the ﬁfth pipeline stage. Obviously,those operations will not involvewriting anything
to the register ﬁle.
A) Explain your modiﬁcations in 3-5 clear sentences.
B) On acopyofFigure 4.60, showthe modiﬁcations. If there isn’tenough room on the ﬁgure to
showthe modiﬁcations, just indicate the locations of the modiﬁcations on the ﬁgure and show
the details separately.Ifyou add anynew modules, you must showtheir implementation in
detail. However, you do not need to showthe implementation of anynew simple MUXes or
registers. Clearly state anyassumptions you make.
C) List all the required newcontrol signals with an explanation and identify them on the datapath
D) Changes are required to the main Control circuit. Showthose changes using a table similar to
the one shown on slide 7.30 in the class notes.
(4) Consider a16M × 1DRAM chip. The notation used belowis: read 100 is a read operation that
reads one bit from address 100, wr ite 350 is a write operation that writes one bit from address 350.
One of twopossible sequences of operations are performed:
A) read 50, read 500, read 5000 B) write 50, write 500, write 500
Which sequence of operations (A or B) can be completed faster ? Explain your answer.
(5) You have 16M × 8DRAM chips (as manyasyou want). You must use these chips to build the data
memory for the single-cycle MIPS processor described in chapter 4ofthe textbook. What is the
minimum size memory you can build ? Specify the size in bits.Explain your answer.