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MIPS代写 | CS151B/EE116C – Homework #6

MIPS代写 | CS151B/EE116C – Homework #6

本次美国代写主要为MIPS相关的Homework,分为Reading Assignment 和 Problem解答两个部分

Reading Assignment:
•Readings from hw #5
Chapter 6, of the 4th Edition:pp. 570-572, 575-590 (input-output). We will refer to this chapter as
Note: This is from the Fourth Edition of the Patterson & Hennessy book. This chapter is available
in the ‘‘Supplementary Readings’’part of the class website as ‘‘The Input/Output Subsystem. ’’
Chapter 7, in the textbook by Hamacher,etal.: pp. 228-229.
Note: This is available in the ‘‘Supplementary Readings’’onthe class website, under ‘‘I/O Bus
Structure. ’’
Chapter 5: pp. 399-401 (‘‘Disk Memory’’).
•Chapter 4: pp. 337-344 (‘‘implementing exceptions in the pipelined MIPS’’).
•Wewill use some material from chapter 8 of the 2nd edition of the Patterson and Hennessy book. We
will refer to this as Ed2-Chap8.This material is available on the class website in the ‘‘Supplementary
Readings’’section of the class website as ‘‘Supplementary material on I/O. ’’
− Ed2-Chap8: pp. 646-647 (‘‘Magnetic Disks’’)
− Ed2-Chap8: 656-659 (ignore figures 8.7 and 8.8)
− The examples in Ed2-Chap8: pp. 676-682
− Ed2-Chap8: pp. 662-673
•Preparation for next week:
Ed4-Chap6: pp. 590-595.
Appendix A: pp. A-641 − A-645 (Exceptions and Interrupts on MIPS).
Chapter 7, in the textbook by Hamacher,etal.: pp. 258-259.
Note: This is available in the ‘‘Supplementary Readings’’onthe class website, under ‘‘PCI Express. ’’
(1) A disk has an average seek time of 4.5ms and rotates at 7,200 RPM. There are 900 sectors per track.
Howlong (in seconds) does it taketoread the data from twoconsecutive sectors on the same track?
Explain your answer.
(2) Consider asystem where all I/O is done using programmed I/O. The I/O device, CPU, and memory
are connected to the same data bus. The data bus is 64 bits wide. It takes 12 nanoseconds for one
transfer across the bus. What is the maximum possible bandwidth (in bytes per seconds) at which
data can be transferred from the I/O device to memory?Explain your answer !

(3) A program repeatedly performs a three-step process: it reads in a 4KB block of data from disk, does
some processing on that data, and then writes out the result as another 4KB block elsewhere on the
disk. Each block is contiguous and randomly located on a single track on the disk. The disk drive
rotates at 7,200 RPM, has an average seek time of 5.2ms, and has a transfer rate of 95 MB/sec. The
controller overhead is 0.3ms. No other program is using the disk or processor,and there is no
overlapping of disk operation with processing. The processing step takes 25 million clock cycles,
and the clock rate is 2.8GHz. What is the overall speed of the system in blocks processed per
(4) An important advantage of interrupts overpolling is the ability of the processor to perform other
tasks while waiting for communication from an I/O device. Suppose that a 2.4GHz processor needs
to read 2000 bytes of data from a particular I/O device. The I/O device supplies 1 byte of data every
0.03 ms. The code to process the data and store it in a buffer takes 1100 cycles.

A) If the processor detects that a byte of data is ready through polling, and a polling iteration takes
60 cycles, howmanycycles does the entire operation take?
B) If instead, the processor is interrupted when a byte is ready,and the processor spends the time
between interrupts on another task, howmanycycles of this other task can the processor
complete while the I/O communication is taking place? The overhead for handling an interrupt is
210 cycles.
Clearly state your assumptions.
(5) A pipelined MIPS implementation with support for overflowexceptions is described in the book, pp.
339-343. Consider the following claim: The description in the book is incomplete since it fails to
modify the operation of the Forwarding unit when an exception occurs.
A) Is the claim above correct ? Your answer must be Yes or No.
B) Explain your answer to Part A.
(6) Consider the pipelined MIPS implementation shown in slides 9.30-9.32 and explained in the book,
pp. 339-343. Your task is to enhance this implementation to add support for the illegalopcode
exception. As described on page 339, the Cause register must be modified based on whether the
exception is an illegalopcode (value 10) or an overflow(value 12). Your implementation must work
correctly evenfor the case where one instruction causes an overflowwhile the very next instruction
contains an illegalopcode.
A) Provide a list of your modifications, where each one of the modifications is described in 1-2 clear
B) The existing datapath implementation is shown on slide 9.30 (available in the Useful Figures
section of the course website). Are anymodification to this figure required?Ifso, you can show
them on a copyofthe figure from slide 9.30. If there isn’tenough room on the figure to showthe
modifications, just indicate the location of the modifications on the figure and showthe details
C) Are anynew control signals required?Ifso, list them with an explanation and identify them on
the datapath diagram.
D) Changes are required to the main Control circuit. Showthose changes using a table similar to the
one shown on slide 9.32. The contents of the table you provide must reflect correct operation
when there are no exceptions, when there is an overflowexception, when there is an illegal
opcode exception, and when overflowand illegalopcode exceptions are detected simultaneously.