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MIPS代写 | CS151B/EE116C – Homework #5

MIPS代写 | CS151B/EE116C – Homework #5

本次北美CS代写主要内容是MIPS相关

CS151B/EE116C – Homework #5, Due 5/3/2021 (no late homeworks)

Further details regarding the exam procedures will be provided separately.
During the exam you will be able to use: the course textbook (6th Edition), the class notes posted on
the class web page, a computer to run LibreOffice as well as retrieve and submit the exam, and a
calculator (software or hardware). Use of any other material is cheating.
You must complete the exam entirely on your own. Getting help from anybody is cheating.
You are ‘‘responsible’’ for all the reading assignments, the class notes, the homeworks, as well as for
everything covered in lectures and discussion sections.
The midterm will cover all the material up to, and including, pipelining.

Reading Assignment:
• Section 2.23, pp. 2.23-2 − 2.23-6. This material can be found on the textbook web site. A copy is also
available in the ‘‘Supplementary Readings’’ part of the class web page.
• ‘‘Instruction Set Styles’’ and ‘‘The IBM/Motorola PowerPC’’ from the 3rd Edition of the book. This
material is available in the ‘‘Supplementary Readings’’ part of the class web page.
• Chapter 6, of the 4th Edition: pp. 570-572, 582-590 (input-output).
Note: This is from the Fourth Edition of the Patterson & Hennessy book. This chapter is available in
the ‘‘Supplementary Readings’’ part of the class website as ‘‘The Input/Output Subsystem.’’
• Chapter 7, in the textbook by Hamacher, et al.: pp. 228-229.
Note: This is available in the ‘‘Supplementary Readings’’ on the class website, under ‘‘I/O Bus
Structure and PCI Express.’’
• Chapter 5: pp. 399-401 (‘‘Disk Memory’’).
• Preparation for next week:
Chapter 4: pp. 337-344 (‘‘implementing exceptions in the pipelined MIPS’’).

Problems:
(1) Consider the pipelined MIPS implementation shown in Figure 4.51 (page 316). The value of the
PCSrcsignal is computed in the MEM stage. Could the PCSrcsignal be computed in the EX stage
instead ? If so, what would be the advantages of making this change ? Also, what would be the
disadvantages of making this change?

(2) Consider the pipelined MIPS implementation shown in Figure 4.51 (page 316). Consider each of the
following two instructions separately:

a. lw $14,60($5)

b. beq $8,$8,400

For each of these instructions (separately), what is the value of the PCSrc signal when the
instruction is in the MEM pipeline stage ? Explain your answer.

(3) Consider executing the following code on the pipelined datapath of Figure 4.60 on page 328:
add $2, $3, $1
sub $4, $3, $5
add $5, $3, $7
add $7, $6, $1
add $8, $2, $6

During the fifth cycle, which registers of the register file are read and which register of the register
file is written?

(4) Figure 4.65 (page 337) shows the pipelined MIPS implementation with the details of how stalls due
to the lw and beq instructions are implemented. As discussed in class, the book doesn’t fully

 

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