本次美国代写主要为MIPS的assignment

Problems:

(1) Consider the pipelined MIPS implementation shown in Figure 4.51 (page 316). The value of the

PCSrc signal is computed in the MEM stage. Could the PCSrc signal be computed in the EX stage

instead ? If so, what would be the advantages of making this change?Also, what would be the

disadvantages of making this change?

(2) Consider the pipelined MIPS implementation shown in Figure 4.51 (page 316). Consider each of the

following twoinstructions separately:

a. lw $14,60($5)

b. beq $8,$8,400

Foreach of these instructions (separately), what is the value of the PCSrc signal when the

instruction is in the MEM pipeline stage?Explain your answer.

(3) Consider executing the following code on the pipelined datapath of Figure 4.60 on page 328:

add $2, $3, $1

sub $4, $3, $5

add $5, $3, $7

add $7, $6, $1

add $8, $2, $6

During the ﬁfth cycle, which registers of the register ﬁle are read and which register of the register

ﬁle is written?

(4) Figure 4.65 (page 337) shows the pipelined MIPS implementation with the details of howstalls due

to the lw and beq instructions are implemented. As discussed in class, the book doesn’tfully

explain howthe stalls for beq are implemented. Assume that the implementation is as shown on

slide 7.55 in the class notes.

As shown in Figure 4.65, the IF/ID register is a selectively-modiﬁed register.Assume that this

register is implemented with ﬂip-ﬂops, as shown on the right side of slide 5.19 in the class notes.

A) On acopyofFigure 4.65, showthe digital circuit (gate-levelimplementation) that generates the

IF.Flush signal. Be sure that it is clear exactly howitisconnected to the rest of the

implementation. If it is connected to a module that generates multiple outputs, clearly identify

the speciﬁc output to which your circuit is connected.

B) Giventhe assumption above reg arding howthe IF/ID register is implemented, showthe digital

circuit (gate-levelimplementation) that uses the IF.Flush signal to implement the desired

functionality.Note that this part should be shown separately from the copyofFigure 4.65.

(5) Problem 4.28.6 in the book.

Note: The information for this problem is provided in Problem 4.28. See practice problem 11 and it’s

solution.

(6) Problem 4.29.3 in the book.

Note: The information for this problem is provided in Problem 4.29. See practice problems 12,13

and their solutions.

(7) An ISA that is very similar to the MIPS ISA supports 120 opcodes and 64 registers. Instructions are

32 bits wide. There is a class of instructions in this ISA that specify tworegister arguments and one

signed (2’scomplement) immediate. What is the maximum possible range of values of this

immediate ?

(8) Problem 2.57 in the supplementary readings: ‘‘The IBM/Motorola PowerPC. ’’ Assume that a[] and

b[] are arrays of 4-byte ints.

Practice problems: Youdonot need to hand in a solution to the problems below.

(9) Consider the pipelined MIPS implementation shown in Figure 4.60 (page 328), with the hazard detection logic

described on page 326.

Consider only the following subset of the MIPS instruction set:

add, addi, sub, subi, and, andi, or, ori, slt, lw, sw

Assume that anyforwarding that can be implemented, is implemented (don’tworry about exactly howitis

implemented).

A) Is the speciﬁed hazard detection and stall implementation logic (Figure 4.60 plus page 326) sufﬁcient to

ensure correct operation?Explain your answer.

B) Claim: The speciﬁed hazard detection and stall implementation logic (Figure 4.60 plus page 326) is not

optimal in terms of performance.

I) Explain whythis claim is correct.

II) Fix anydeﬁciencies in the hazard detection and stall implementation logic. Speciﬁcally,ifFigure

4.60 needs to be modiﬁed, showthe modiﬁed ﬁgure. If the logic described on page 326 needs to be

modiﬁed, provide the corrected description.

III) Are the changes made in part (II) likely to have a signiﬁcant impact on performance?Explain your

answer.

(10) Consider the pipelined MIPS implementation shown in Figure 4.51 (page 316).

Figure 4.51 includes support for the beq instruction. However, Figures 4.51 ignores the existence of control

dependencies. Speciﬁcally,Figure 4.51 does not include the required control hazard detection and stall

implementation.