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C语言代写 | ECE 449/533 – Computer Design Pipeline the DLX architecture

C语言代写 | ECE 449/533 – Computer Design Pipeline the DLX architecture


ECE 449/533 – Computer Design
Spring 2020
Pipeline the DLX architecture
Purpose: The objective of this lab is to understand a simple unpipelined DLX architecture
simulator and to then pipeline the system.
In order to simulate a pipelined processor, you will need to add five pipeline stages into the
simulator as defined in Chapter 4. Each pipeline stage should be modeled in a separate
function call from the main simulator loop in sim.c (in other words, these five function calls
will replace the simulate_DLX_cycle call). You will need to add pipeline registers between
each pipeline stage.
The simulator WILL implement data forwarding. It will detect data and control hazards.
Control instructions are to be resolved in the decode phase.
You can check your simulator by comparing the final register values of the unpipelined
simulator with your pipelined version. Five programs prog1 to prog5 are provided to you for
testing. Additionally you can install the winmips64 simulator in under windows
to examine see how instructions should be handled. To use winmips64, run the equivalent
program files in in this simulator.
To turn in: Each student is required to upload their code by Tuesday, April 7, 2020 at
11:55pm to Isidore.
Three files should be uploaded: sim.c, assemble.c, and globals.h.
Collaboration: Work turned in for this lab and for all others throughout the semester must be
completed by each individual student.