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C语言代写 | CS 252 Computer Organization Simulation #4 Single-Cycle CPU

C语言代写 | CS 252 Computer Organization Simulation #4 Single-Cycle CPU


1 Purpose

In this project, you will implement a single-cycle CPU. One of the keys of this
project is understanding how the control bits are used to direct the rest of the
processor – so most of your code will be finding (and then using) the various
control bits.

Unfortunately, in order to test that you are doing this correctly (without
having the TAs spend hours looking at your code), I had to break the CPU
down into a fairly large number of relatively small pieces. You will implement
a number of functions – most will be fairly small – and my testcases will join all
of the little pieces together into a larger system.

You’ll be happy to learn that in this project, I have removed the restric-
tions! Now, if you want to add, multiply, or whatever, you are allowed to do
it. We can allow this now because now you know what it takes – something
as simple as the + operator in C actually represents a non-trivial component in

We’ll be writing this project entirely in C.

1.1 \Extra” Instructions and Their Testcases

There are a certain set of instructions which all students must implement – ba-
sically, these are the set which can be easily implemented by the basic processor
design that we’ve provided for you.

However, you will also be expected to expand on this design a bit. We
have provided a set of \extra” instructions, which can also be implemented
with (relatively) small changes to the processor. You must choose three of these
instructions, and update your design to support them (details below).

When you download the testcases for your program, you should download the
\ordinary” testcases (they are all numbered), and then download the \extra”
testcases for the instructions that you have chosen. Test them all using the
grading script.

1.2 Required Filenames to Turn in

The first required file is a C file; name it sim4.c.
In addition, turn in a README file – it must be a text file. Name it README
or README.txt. The first paragraph of this file should simply list the \extra”
instructions you have chosen to implement1. The rest of the README

file should describe how you changed the processor to support them.
We’ll use this README file to (manually) configure the grading script for
you – so please, follow the instructions. We don’t want to have to search through
100 different student directories for hard-to-read README files!

1.3 More Complex Testcases

Because the testcases have a lot of C code that they share, I now have some
\common code” which is shared across all of them. This is contained in a header
file sim4 test commonCode.h and the matching source file sim4 test commonCode.c.
Each testcase will include the header, and link with the shared code.

While you are allowed to include the test-common-code header if you want,
I don’t think that you will need it. Feel free to poke around the code, however.

1.4 Random Numbers

Please note that testcase 08 uses C’s rand() function to generate inputs. The
.out file that I have provided works when running on Lectura, but it may or
may not work on your machine. If you are failing testcase 08, try running it on
Lectura instead.

2 \Ordinary” Instructions

Your CPU must support all of the following instructions:

add, addu, sub, subu, addi, addiu

(Treat the ‘u’ instructions exactly the same as their more ordinary counter-
parts. Just use C addition and subtraction, using signed integers. Ignore
over ow.)

and, or, xor2
slt, slti
lw, sw
beq, j

The testcases will handle the syscall instruction on your behalf – you don’t
have to write any code to make it work.

Your implementation for these instructions must match the book
– and the slides we’ve been going over in lecture. You must use the same
control wires, with the same meanings. Your \extra” control wires (if any)
must all be zero for these instructions.

2.1 \Extra” Instructions

Choose three instructions from the following list (no more than one from
each group below!), and implement them as well in your CPU:

andi, ori, xori, nor
sra, srl, sll
srav, srlv, sllv
lb, sb
mult, div4
mfhi, mflo

Your implementation for these instructions must match the MIPS architec-
ture; you can look each of these up, in Appendix A, to find out exactly how they
work. You must use the opcode that MIPS requires, and do exactly
what the MIPS architecture says these instructions do.

However, none of these can be implemented with the standard CPU design
that we’ve discussed. Each one needs some sort of small change. Some can
be implemented by adding a new ALU operation, or by adding a new input to
an existing MUX; others will require that you add a new MUX, or new logic
somewhere in the processor.