这是一篇来自日本的关于RISC-V处理器的代码代写
Details
Reminders:
Please update Logisim for this project (if you are running an older version a prompt should automatically appear on launch to update). A bug affffecting the testing process for this project has been fifixed, and it is crucial that you are working on the updated version. Always make sure to update your Logisim when prompted. If your internet connection is limited by some form of geo-restriction that limits access to Google or Github (such as the great fifirewall), you will need to re-download the .jar from Canvas (resources page).
This is an individual project. Do not show your work to anyone or look at the work of anyone.
NOTE:
please update your logisim before starting this project!
Overview
In this project, you’ll implement a single-cycle processor in Logisim. Your processor will support a small subset of the RISCV instruction set, including arithmetic, logic and memory operations. You’ll also write a test fifile and a small byte reversal program, both in RISCV, to ensure your processor’s correctness.
Since this project requires you to understand the overall layout and functionality of the processor in depth, we recommend meeting with a TA during your lab section to talk through your design and answer any questions you may have.
Academic Integrity: As one of the most widely studied architectures, RISCV has a wealth of information available on the web and in textbooks. Feel free to use any RISCV documentation you fifind to help you learn how the instructions work–but make sure your design is your own. If you’re unsure if it’s okay to borrow from a source, ask the TAs. Please cite any signifificant outside source you use that wasn’t provided to you by us. And, of course, make sure your information is accurate! When in doubt, the offiffifficial RISCV manual (https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-
v2.2.pdf) is your best bet.
What To Submit
An assembly program containing your byte reversal implementation.
A single Logisim project fifile (extension: .circ) containing your processor and all needed subcomponents.
A text fifile containing your well-commented RISCV assembly test program.
Heads up! Last semester, students who fifilled out the survey reported the following:
Instructions
Your processor must support the following instructions:
Format
Instructions
R-type
ADD, SUB, AND, OR, XOR, SLT,SLL, SRA
I-type ADDI, ANDI, LW, LB
S-type SW, SB
U-type LUI
Check the RISCV manual (https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf) to see how these instructions are laid out in binary and what they do. Page 104 provides a helpful table for comparing the formats side by side.
We won’t test your processor with any instructions not in the list above. You do not have to implement or account for them in any way – their behavior can be undefifined and up to your discretion.
Byte Reversal
Important: just to be sure, make sure you do not base your submission’s correctness on ##start statements in the byte reversal part, as we will not take them into consideration during grading. ##expect statements on the other hand should be fifine since they do not change the state of the processor. We will not accept “trivial” answers that simply use register pre-setting to implement “byte reversal.”
To introduce to you (and hopefully better familiarize yourself with) the RISC-V assembly instructions, you will create your very own byte reversal program using the instructions that you will later implement for your processor in Logisim.
Byte reversal changes the order of bytes in a word, in our case a word consists of 32 bits or 4 bytes. A word that is made up of the four bytes
A | B | C | D will end up as D | C | B | A after being reversed. In hexadecimal notation a byte is written as two digits, so a byte reversal of a word, e.g. 0xABCDEF01 , would look like this; 0x01EFCDAB . Note that the order of bits in the bytes does not change.
We will have you try out two ways of doing this in assembly; using bitmasks and using the load and store byte instructions. We highly recommend you test your program on the RISCV interpreter
(https://www.cs.cornell.edu/courses/cs3410/2019sp/riscv/interpreter/) as well to see if your processor demonstrates the expected behaviour.
A bitmask is a number that can be used to select, discard, set or flflip certain bits of a value. The easiest way to understand what a bitmask does is by looking at an example in binary, although bitmasks can be written in other notations as well.
Mask: 00001111
Value: 01010101
ANDing the mask and the value will preserve set bits in the lower four bits while discarding the upper four ones
Result: 00000101
ORing the mask and the value will combine the mask and the value by setting the lower four bits of the value while not affffecting the upper four bits
Result: 01011111
XORing the mask and the value will flflip the lower four bits of the value while not affffecting the upper four bits
Result: 01011010
For the fifirst part of the program you will need to construct bitmasks in order to select the individual bytes. These selected bytes can then be shifted to their new position in the word and combined to form the reversed word. Since a byte is 8 bits you will be shifting the bytes to their new positions by multiples of 8.
Tip: LUI is a useful instruction to set the upper 20 bits in a word, ADDI will only allow you to set the lower 12 bits. Using both instructions you can create a 32 bit number 🙂
Load Byte, Store Byte
These instructions allow you to access and store single bytes in memory. You can reverse the order of a word in memory by loading the bytes individually and storing them in a reverse order. You can then load the reversed word from memory with Submission
Download the template for your program here: P2-byte-reversal.txt
(https://canvas.cornell.edu/courses/42905/fifiles/6057626/download?wrap=1)
(https://canvas.cornell.edu/courses/42905/fifiles/6057626/download?download_frd=1) .
Your program will consist of three parts:
- Reverse the word 0x12345678 at memory address 0 using bitmasks, store the result in t0 (x5)
Expected value in t0: 0x78563412
- Reverse the word 0x13f4464c at memory address 4 exclusively using the instructions LB and SB, store the result in t1 (x6). You may use LW to load the reversed word into a register.
Expected value in t1: 0x4c46f413
- XOR both reversed words from 1. and 2. and store the result in t2 (x7)
Implementation
Logisim Dos and Don’ts
Make sure your Logisim version is up-to-date with the version listed at the top of this page.
Build your RISCV processor as a single Logisim circuit fifile. Do not use Logisim’s Project > Load Library > Logisim Library command to import circuits from other Logisim fifiles.
Your top-level circuit must be named “RISCV” or “RISCV32” (case-sensitive).
exactly one of each component, excluding the LCD video and Core (yes, that means only one incrementer). Do not nest these components any deeper than one subcircuit down.
Feel free to use other regular Logisim components, with the following caveats:
- The only component in the Memory folder that you should use is the register.
- The Arithmetic folder is forbidden.
- Components at the transistor level or below (e.g. transistor, power, ground, transmission gate) are forbidden.
- Constants are forbidden.
- You can use tunnels, but if you do, please use sparingly for the sake of readability.
- Avoid empty inputs/outputs on splitters and plexers.
- You may only use one clock. Subcircuits requiring a clock signal should use input pins to connect to the processor clock. Each cycle should begin on a rising clock edge
We encourage you to also take a peek at the Not sure how to start? and Help and Hints section near the bottom of this writeup before starting your circuit as you might fifind it to be incredibly helpful and also answer some initial questions regarding the processor.
