1. [Pass-Transistor Logic and Transmission Gate] Consider the following expression:
(a) Use the complementary CMOS to implement the above function. Derive the expressions for
both pull-down and pull-up networks, and draw the schematic of the digital circuit.
(b) The pass transistor sometimes can be used to reduce the number of transistors when
implementing a specific function. For the circuit you designed in (a), try to use the pass
transistors to improve the design, such that the total number of transistors is no more than 10.
Hint: Figure 1 shows the solution of simplifying the PDN. You can start with analyzing the
difference between the original PDN. Think about why pass transistor can enable the sharing of
paths. And finally create PUN to complete the design.
(c) Then just use the transmission gates to implement the function of following expression. You are
allowed to directly use A , B, … as inputs.
Hint: You can write the truth table first and implement the circuit that exactly follows the truth
table in a straightforward way.
2. [Sequential Logic] The schematic and truth table of clocked SR latch is shown below.
(a) Consider the clocked JK latch showing below, write the truth table and analyze the improvement
compared with the clocked SR latch.
(b) Consider the master-slave JK flip-flop showing below, write the truth table and analyze the
improvement compared with the clocked JK latch. (in the table, “_Π_” means clock pulse)
(c) Modify the schematic of master-slave JK flip-flop so that it can implement the function of D flip-
(d) Compare the D flip-flop you implemented in (c) and the one introduced in the lecture. Which
one is better? Explain the reason.
Hint: Analyze the situation that there is a disturbance at the input when Clk=1.