1. Assume an inverter in generic 0.25𝜇m CMOS technology designed with a PMOS/NMOS
ratio of 3.4 and with the NMOS transistor minimum size (𝑊𝑊 = 0.375𝜇m, 𝐿𝐿 = 0.25𝜇m, 𝑊𝑊/𝐿𝐿 =
1.5). We also know the switching threshold 𝑉𝑉𝑀𝑀 = 1.25𝑉𝑉, supply voltage 𝑉𝑉𝐷𝐷𝐷𝐷 = 2.5𝑉𝑉, and other
parameters as shown in Table 1. Approximating the inverter’s voltage-transfer curve by linearizing
the slope at the threshold, please calculate the 𝑉𝑉𝐼𝐼𝐼𝐼, 𝑉𝑉𝐼𝐼𝐼𝐼, 𝑁𝑁𝑁𝑁𝐼𝐼, 𝑁𝑁𝑁𝑁𝐼𝐼.
Hint: In week3b slide #23, 𝑔𝑔 is gain at the switching threshold 𝑉𝑉𝑀𝑀. To calculate 𝑔𝑔, you may want
to utilize the drain-source current relationship between PMOS and NMOS.
Note: 𝑘𝑘𝑛𝑛′= 𝜇𝜇𝑛𝑛𝐶𝐶𝑜𝑜𝑜𝑜,𝑛𝑛, 𝑘𝑘𝑝𝑝′= 𝜇𝜇𝑝𝑝𝐶𝐶𝑜𝑜𝑜𝑜,𝑝𝑝, channel-length modulation effect should be
In this problem, we will analyze the noise margins for chains of gates.
a) First, let’s consider Figure 1(a). Add to the chain the DC voltage sources that you would use for
modeling noise coupling to the input and output of gate M2. You should arrange these voltage
sources so that they would both impact the noise margin in the same way (i.e., if the voltage source
at the input decreases the noise margin, the voltage source at the output should also decrease the
b) Figure 1(b) shows the VTC of gates M1, M2, M3, respectively. For each stand-alone gate:
i. Compute the numerical values in Volts of the noise margins (that is, 𝑁𝑁𝑁𝑁𝐼𝐼 and 𝑁𝑁𝑁𝑁𝐼𝐼).
ii. Draw the butterfly diagram of the gate. (Hint: butterfly diagram is the VTC diagram to
show the regenerative property)
iii. Determine whether the gate is digital or not. (Hint: being “digital” requires the gate be
c) Now consider only the cascade of M2 and M3. For this part:
i. Determine the VTC of the cascade.
ii. Compute the numerical values in Volts of the noise margins.
iii. Determine whether the cascade of the two gates is digital or not.