Standard circuitry (encoder, decoder mux), combinatorial circuit design
These problems do not need to be submitted – they are easier and can help prepare/familiarize the student with the
material on the harder problems (that do need to be turned in).
1. Build a MUX from a Decoder and some AND and OR gates
2. A MUX-with-Enable is a MUX with one additional selector input, E. When E = 1, the MUX-with-Enable
behaves like a traditional MUX. When E = 0, the MUX-with-Enable is disabled and outputs 0. Build a MUX
with-Enable from a MUX (without enable) and some AND gates.
3. A 1-to-2k DEMUX takes one data input I and a k-bit selector S as input and outputs 0 on each of 2k −1 outputs,
and outputs I on the jth output where j is the unsigned binary value represented by S. Construct a DEMUX
from a decoder and a bunch of AND gates.
4. Use five 2-to-1 MUXs and as many NOT gates as needed, buid a circuit that take a 5-bit value and a selector
input S and returns
• when S = 0, the original number is returned
• when S = 1, the 1’s complement of the number is returned.
5. Build a circuit using two 2-to-1 MUXs that takes a 2 bit-input B1B0 and a 1-bit selector S and returns B1B0
when S = 0 and returns B0B1 (i.e., switches the bit-order) when S = 1.
6. Solve problem 3 of the “Harder Problems” using four 16-to-1 MUXs, one MUX for each output NSH, NSL,
EWH, EWL. Now solve using four 8-to-1 MUXs
7. Design a circuit that receives a k-bit string A = Ak−1Ak−2 · · · A1A0 and, using k − 2 4-to-1 MUXs, outputs
k-bit string B = Bk−1Bk−2 · · · B1B0 with the following properties
• B0 = A0; Bk−1 = Ak−1
• Bi = Ai whenever Ai+1 6= Ai−1; 0 < i < k − 1
• Bi = Ai−1 whenever Ai+1 = Ai−1; 0 < i < k − 1
1. Construct a 4-to-16 line decoder with an enable input using five 2-to-4 line decoders with enable inputs (Hint:
Start at the outputs: If all that is being used is decoders, then how many decoders are connected directly to
2. A combinatorial circuit is specified by the following three Boolean functions:
F = X + Y¯ + XY Z ¯
Design the circuit with a decoder and external OR gates.