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计算机代写|CMPEN 331 – Computer Organization and Design Lab 5

计算机代写|CMPEN 331 – Computer Organization and Design Lab 5



This lab introduces the idea of the pipelining technique for building a fast CPU. The students will obtain experience with the design implementation and testing of the first four stages (Instruction Fetch, Instruction Decode, Instruction Execute, Memory) of the five-stage pipelined CPU using the Xilinx design package for FPGAs. It is assumed that students are familiar with the operation of the Xilinx design package for Field Programmable Gate Arrays (FPGAs) through the Xilinix tutorial available in the class website.

  1. Pipelining

As described in lab 4

  1. Circuits of the Instruction Fetch Stage

As described in lab 4

  1. Circuits of the Instruction Decode Stage

As described in lab 4

  1. Circuits of the Execution Stage

As described in lab 5

  1. Circuits of the Memory Access Stage

As described in lab 5

  1. Circuits of the Write Back Stage

Referring to Figure 1, in the fifth cycle the first instruction entered the WB stage. The memory data is selected and will be written into the register file at the end of the cycle. All the control signal have a prefix “w”. The second instruction entered the MEM stage; the third instruction entered the EXE stage; the fourth instruction is being decoded in the ID stage; and the fifth instruction is being fetched in the IF stage. All the six pipeline registers are updated at the end of the cycle (the destination register is considered as the six pipeline register).

Then the first instruction is committed. In each of the forth coming clock cycles, an instruction will be committed and a new instruction will enter the pipeline. We use the structure shown in Figure 1 as a baseline for the design of our pipelined CPU.

  1. Table 1 lists the names and usages of the 32 registers in the register file.
  2. Write a Verilog code that implement the following instructions using the design shown in Figure 1. Write aTable 2 lists some MIPS instructions that will be implemented in our CPU
    1. Initialize the first 10 words of the Data memory with the following HEX values:











    1. Verilog test bench to verify your code: (You have to show all the signals written into and out from the MEM/WB register and the inputs to the Regfile block in your simulation outputs)



    lw $2, 00($1)

    # $2 ß memory[$1+00]; load x[0]

    lw $3, 04($1)

    # $3 ß memory[$1+04]; load x[1]

    lw $4, 08($1)

    # $4 ß memory[$1+08]; load x[2]

    lw $5, 12($1)

    # $5 ß memory[$1+12]; load x[3]

    add $6, $2, $10

  1. Write a report that contains the following:
  2. Your Verilog design code. Use:
  3. Device: XC7Z010- CLG400 -1 or choose any other FPGA type. You can use Arria II if you are using Quartus II software.
  1. Your Verilog® Test Bench design code. Add “`timescale 1ns/1ps” as the first line of your test bench file.
  2. The waveforms resulting from the verification of your design with ModelSim showing all the signals written in and out from the MEM/WB register and the inputs to the Regfile block.
  1. The design schematics from the Xilinx synthesis of your design. Do not use any area constraints.
  2. Snapshot of the I/O Planning and
  3. Snapshot of the floor planning
  4. REPORT FORMAT: Free form, but it must be:
  5. One report per student.
  6. Have a cover sheet with identification: Title, Class, Your Name, etc.
  7. Using Microsoft word and it should be uploaded in word format not PDF. If you know LaTex, you should upload the Tex file in addition to the PDF file.
  1. Double spaced
  2. You have to upload the whole project design file zipped with the word file.
  3. For students who took this class as an (honor option). In addition to all of the above requirements,you need to design the following:

In order to focus our attention on the WB stage easily, the baseline CPU shown in Figure 1 is redrawn by putting the register file on the WB stage where the execution result of an instruction is written as shown in Figure 2. The state of the art content can be read correctly in the ID stage after it is written at the end of its WB stage. Data hazards occur in the code example shown in Figure 3. You need to add the required components to solve the hazard problem and do forwarding if needed.