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数字电路代写 | Digital Systems electronics – Written test – Part 2

数字电路代写 | Digital Systems electronics – Written test – Part 2


1. A digital system receives a stream of unsigned samples, x(n). At each discrete time n, the circuit has to calculate the
average value of the sample sequence x(n-6), x(n-4), x(n-2), x(n). The first valid output must be generated starting
from time n=6, i.e. after receiving the seventh sample.
Inputs: start START, clock CK, synchronous reset RST, input sample x.

Outputs: calculated average AVG, validation signal VAL.

Behaviour: the system is in idle state as long as START=0. When START=1 on the rising edge of CK, the system must
read the first sample on the following rising edge of CK. At every successive clock cycle, a new input sample is
received. When a new average is ready, the system must raise the output VAL and, at the same time, it must drive
the output data port AVG with the calculated value value. When START=0, the system goes back to the idle condition
and waits for a new stream of samples.

Requested elements:

A. Draw the datapath of the system, using elementary components as registers, adders, multipliers, …
B. For each datapath component, clearly show the input and output data, as well as the control signals
C. List all control and status signals
D. Draw the control unit as a FSM (only the state diagram is requested), clearly showing received inputs and
driven outputs
E. Write the VHDL code of the FSM (architecture part only)

2. Design a circuit able to generate the sequence of prime numbers from 1 up to 7. The circuit must support the
following operations: reset (i.e. jump to 1), hold current value, increment (i.e. jump to the next prime number). If
the current output is 7 and the increment command is received, the circuit moves to 1.

Requested elements:

A. Detail the overall structure of the circuit in terms of flip flops and elementary gates
B. Derive the maximum clock frequency as a function of the propagation delay of the allocated components
C. (OPTIONAL) Provide the behavioural VHDL description (architecture part).

4. Develop an application for the STM32 MCU able to drive an external LED with the following repeated sequence of
pulses: one pulse, two pulses, three pulses, four pulses, three pulses, two pulses, one pulse. Therefore, the period
of the sequence contains seven elements, where element one is formed by a single pulse, element two is formed
by two pulses and so on, up to the seventh element, which includes again a single pulse. At every pulse, the LED is
switched on for 250 ms. Pulses belonging to a single element of the sequence are separated by a 250 ms off state,
while the pauses between two elements of the sequence are 1 s long.

A. Describe the approach you want to use to implement the described application and identify the used
B. List the necessary configuration steps and briefly describe each of them (it is not required here to use
exact names of drivers of registers, just explain what you mean)
C. Provide the code (or pseudo-code) for the infinite loop and/or the interrupt routines (if any).