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代码代写|Laboratory Exercise 7 Memory and the VGA Display

代码代写|Laboratory Exercise 7 Memory and the VGA Display



The purpose of this exercise is to learn how to create and use on-chip block random access memories (BRAMS) as well as use the video graphics adapter (VGA).

1 Workflflow

For each part of the lab, you should begin by writing and testing Verilog code, using Model Sim. Once your design works in simulation, you should compile it with Quartus. You must simulate your circuit with ModelSim using reasonable test vectors written in the format used in Lab 2 for the simulation fifiles. You should be prepared to show schematics, Verilog, and simulations to your TA, if requested. You will not be helped with debugging your code if you do not have schematic and ModelSim simulations. Issues identifified with the tester, without doing your own ModelSim simulations will not get help.

Warning: This lab document is quite detailed and covers a lot of new information. Please read through it carefully. Do not rush to just get the labs done as you will spend much more time debugging your code than making progress. Also, it is highly recommended that you watch the tutorial videos on Quercus in the Lab 7 page.

2 Part I

In addition to lookup tables (LUTs) and flflip flflops, the FPGA provides flflexible embedded memory blocks that can be confifigured into various bit widths and depths along with many other parameters. To access these blocks you will use another feature of Quartus that can build modules of various functions. In this part of the lab exercise you will create a small RAM block and interact with it to understand how it works. Using the Quartus IP catalog  you will fifirst create a module for the desired memory. This will create a module that you can then instantiate in your designs when you need such a memory block. You can test the memory module using ModelSim and, if you have a board, using the switches and HEX displays for inputs and outputs.

The memory module we would like to create is shown in Figure 1. It consists of a memory block, address register, data register and a control register. You can see that the address and input data are stored in a register as well as the Write Enable control signal. Using the registers means that the DataOut value will be stable for one clock cycle and allows the inputs to be changed after the rising clock edge in preparation for the next clock cycle. It is a small memory so that we can easily interact with it using the available switches and displays on the the DE1-SoC board.

Figure 2 shows a timing diagram for reading from the memory. Four locations at addresses A0, A1, A2 and A3 are accessed and the corresponding data D0, D1, D2 and D3 are read from those addresses, respectively. Figure 3 shows the timing for writing data to the memory.

Observe that WriteEn is only high for addresses A1 and A2. This means that only data words D1 and D2 are written, respectively.

To generate the memory module for the small memory shown in Figure 1, perform the following steps.

  1. Open Quartus.
  2. You will now create a memory module that you can include into your design. First, select Tools–>IP Catalog
  1. Open Installed IP–>Library–>Basic Functions–>On Chip Memory–>RAM:1-PORT
  2. Browse to the folder or directory where you want to build your project. This is where the fifile for the memory module will be created. Call the fifile part1.v. Choose the IP variation to be Verilog and click OK.
  1. Select a 4-bit wide (width of ‘q’ output bus) memory with 32 words. Leave the memory block type as Auto and use a Single Clock. Click Next.
  1. Unselect q as a registered port.
  1. Click Finish and Finish again to generate the new Verilog fifile, part1.v.
  2. Examine the newly created Verilog fifile. Observe that it declares a module with the required ports as shown in Figure 1. You can now instantiate the module into any design.
  1. Simulate your part1 module with ModelSim to satisfy yourself that your circuit is working. Be prepared to justify that your test cases are enough to give confifidence that your circuit is working.

Since you are adding the BRAM IP to your project, you will need to add an additional parameter to simulate this. The following shows how to do this in your Modelsim


vsim -L altera_mf_ver <module-name>

For some more information on what this does, read Section 4 below. When you are satisfified with your simulations, you can submit to the Automarker.

  1. Create a new Quartus project for your circuit. You will need a top-level module to make connections from the instantiation of your part1 module to the switches, pushbutton and HEX displays of the DE1-SoC board. The connections used are shown in Table 1.