The two Components of Register File access time are:
(i) Address input → WL select and (ii) WL select to D_out.
(1) Assuming the 8KB (64Kbit) array we discussed in class during Week 7, design a static CMOS gatebased decoder that implements a 7-bit address decoder to select one of 8 Blocks and one of 16 Word Lines per Block at minimum delay. To determine the load at the end of the decode network (Cap of WL) Assume all 256 bitcells along a row are selected by the RWL driver (128 bits on either side of the RWL driver placed between 2 blocks each of which is 128b wide in the Word direction and 16b tall in the BL direction).
(2) Characterize the delay of the bitpath: WL select → D_out assuming the Domino Read architecture (slides 13-15 in Lec 7) for local bit lines at 16b and 32b lengths (corresponding to 8Blocks or 4 Blocks in(1) above.
Estimate wire lengths between gates along the decode path and bitpath using cell dimensions (Fig 1). Assume cell height of 90nm and a cell width of 360nm
Fig 1: 8T Register File bitcell layout. Use this layout to create a bitcell schematic with the same number of fins per device and determine total input capacitance of the RWL and LBL ports of the bitcell Use array architecture with 8 blocks shown in Fig 2a below to estimate wire lengths of GRBL and R & C values of GRBL (assuming c = 0.185fF/um & r=0.95 ohms/sq where wire width for GRBL can be assumed as = 100nm
Fig 2a: Array architecture of 64Kbit Reg File array
Fig 2b: Local bitpath schematic
Fig 3: An example of a Circuit Schematic for the RWL decoder
Fig 4: Example waveforms along the Word and bitpath
(3) Estimate the total active energy consumed during a read access per bit column. As an approximation,only consider the energy to charge the LBL and GRBL in a sequence of Read accesses.